(110) SURFACE ORIENTATION FOR REDUCING FERMI-LEVEL-PINNING BETWEEN HIGH-K DIELECTRIC AND GROUP III-V COMPOUND SEMICONDUCTOR DEVICE

摘要

PURPOSE: A surface orientation for reducing Fermi level pinning between a high K dielectric and a III-V group compound semiconductor device is provided to balance a charge distribution on a (110) crystallographic orientation surface by the dangling bond of the equivalent number of anions and cations. CONSTITUTION: A III-V compound semiconductor material including a (110) crystallographic orientation surface is provided(310). Natural oxide is removed from the (110) crystallographic orientation surface(320). After the natural oxide is removed, a high K dielectric layer is formed on the (110) crystallographic orientation surface(330). [Reference numerals] (310) Provide a III-V compound semiconductor material including a (110) crystallographic orientation surface; (320) Remove natural oxide on the (110) crystallographic orientation surface; (330) Form a high-k dielectric layer on the (110) crystallographic orientation surface after removing natural oxide