发明名称 Memory with extended charge trapping layer
摘要 A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges.
申请公布号 US8441063(B2) 申请公布日期 2013.05.14
申请号 US20100982006 申请日期 2010.12.30
申请人 FANG SHENQING;CHEN TUNG-SHENG;CHEN CHUN;SPANSION LLC 发明人 FANG SHENQING;CHEN TUNG-SHENG;CHEN CHUN
分类号 H01L29/792;H01L21/336 主分类号 H01L29/792
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