| 摘要 |
Floating point multiply-accumulate (FMAC) instructions are processed by a logic circuit. A register file stores operands for a FMAC instruction. A multiplier multiplies an operand S1 and an operand S2 from the register file to produce a resultant operand St. An adder adds two operands St and Sd (which is the result of a prior accumulation) to produce the result Sd of the FMAC instruction. A reorder buffer (ROB) stores and reorders entries corresponding to FMAC instructions, and a hazard-checking block detects whether the FMAC instruction contains a potential hazard. A selector selects an output value from the ROB. The operands St and Sd can be supplied via one of a plurality of paths based on a priority of the paths, and the priority for the paths is based in part on output from the hazard-checking block and contents of the ROB.
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