| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a ramp signal generation circuit and a ramp signal adjustment circuit which do not change the voltage peak value of a ramp signal when the cycle (frequency) of the ramp signal is varied. <P>SOLUTION: When the cycle of a clock signal S1 fed to an input terminal 21 changes, the respective voltages of input terminals 36, 37, 38, and 39 of a ramp signal generation circuit 5 change to the high (H) or the low (L) level. Since a discharge circuit 19 discharges a capacitor C3 synchronously with the clock signal S1, the frequency of a ramp signal S2 matches that of the clock signal S1. On the other hand, a charge circuit 18 selectively switches between sets of resistive elements R13, R14, R15, and R16 and diodes D3, D4, D5, and D6 in which sets a charge current for the capacitor C3 flows, to change a current value with which the capacitor C3 is charged so that the voltage peak value of the ramp signal S2 will be constant irrespective of the cycle of the clock signal S1. <P>COPYRIGHT: (C)2013,JPO&INPIT |
