SEMICONDUCTOR DEVICE OPERATING ACCORDING TO LATENCY VALUE

摘要

Disclosed herein is a device that includes a first register temporarily storing first information indicative of a reference latency, a second register temporarily storing second information indicative of an offset latency, a third register temporarily storing third information indicative of one of first and second operation modes, and a logic circuit configured to produce latency information in response to the first information when the third information is indicative of the first operation mode and to both of the first information and the second information when the third information is indicative of the second operation mode.