发明名称 SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS
摘要 In one embodiment, the memory device includes a memory cell array, to data line selection circuit and selection control logic. The memory cell array has at least a first memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. The selection control logic is configured to detect if a defective memory cell in the first memory cell group is being accessed, and is configured to control the data line selection circuit to replace access via the first data line with access via the redundancy data line such that a detected defective memory cell in the first memory cell group is replaced with one of the plurality of redundancy memory cells.
申请公布号 US2013117615(A1) 申请公布日期 2013.05.09
申请号 US201213671261 申请日期 2012.11.07
申请人 KIM SU-A;KIM DAE-HYUN;LEE WOO-JIN 发明人 KIM SU-A;KIM DAE-HYUN;LEE WOO-JIN
分类号 G11C29/04 主分类号 G11C29/04
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