发明名称 |
Load Pair Disjoint Facility and Instruction Therefore |
摘要 |
A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses are loads and the disjoint data is stored in general registers.
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申请公布号 |
US2013117546(A1) |
申请公布日期 |
2013.05.09 |
申请号 |
US201213726746 |
申请日期 |
2012.12.26 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
JACOBI CHRISTIAN;MITRAN MARCEL;SLEGEL TIMOTHY J.;WEBB CHARLES F. |
分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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