发明名称 Semiconductor test apparatus and test method
摘要 In a semiconductor test apparatus, a voltage source generates a power supply voltage to be supplied to a DUT. A decision processor makes the DUT execute a predetermined test sequence. A noise generator superimposes a periodic pulse-like noise voltage on the power supply voltage to be supplied to the DUT, while the test sequence is being executed. The noise generator superimposes a noise voltage synchronized with a clock signal to be supplied to the DUT.
申请公布号 US8433990(B2) 申请公布日期 2013.04.30
申请号 US20080602144 申请日期 2008.05.12
申请人 MATSUMOTO MITSUO;ADVANTEST CORPORATION 发明人 MATSUMOTO MITSUO
分类号 G06F11/00 主分类号 G06F11/00
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