发明名称 Asynchronous scheme for clock domain crossing
摘要 Apparatus and methods for clock domain crossing between a first clock domain and a second clock domain. The apparatus comprises a first control logic element for processing a handshake signal and producing a first arbiter input signal. Concurrently a second control logic element processes a second handshake signal and produces a second arbiter input signal. Exemplary embodiments include exactly one arbiter element inputting the first arbiter input signal, inputting the second arbiter input signal, outputting a first clocking signal to the first sequential element and outputting a second clocking signal to the second sequential element. For managing metastability by controlling the timing of the clocking inputs of the sequential devices, the apparatus includes a first controllable lock delay element selected to satisfy the setup constraint of the second sequential element, and a second controllable lock delay element selected to satisfy the hold constraint of the second sequential element.
申请公布号 US8433875(B2) 申请公布日期 2013.04.30
申请号 US20100711909 申请日期 2010.02.24
申请人 CORTADELLA JORDI;LAVAGNO LUCIANO;MACIAN CARLOS;MARTORELL FERRAN;ESILICON CORPORATION 发明人 CORTADELLA JORDI;LAVAGNO LUCIANO;MACIAN CARLOS;MARTORELL FERRAN
分类号 G06F12/00 主分类号 G06F12/00
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