发明名称 Fail safe circuit
摘要 Apparatus for preventing output of an input signal is disclosed. The apparatus comprises a signal control unit comprising a signal buffering unit having an input and an output, the signal buffering unit arranged to receive an input signal and pass the input signal to the output when the signal buffering unit is powered, wherein a negative power supply terminal of the signal buffering unit is arranged to be supplied by a first power source having a voltage. The signal control unit also comprises a boost circuit arranged to boost the voltage of the first power source to a boosted voltage higher than the voltage of the first power source and supply either the voltage of the first power source or the boosted voltage to a positive power supply terminal of the signal buffering unit. The signal buffering unit is powered when the boosted voltage is supplied to the positive power supply terminal of the signal buffering unit and the signal buffering unit is not powered when voltage of the first power supply terminal is supplied to the positive power supply terminal of the signal buffering unit. Also disclosed is an apparatus for providing output voltages for driving a motor as well as a motor drive system.
申请公布号 GB201304187(D0) 申请公布日期 2013.04.24
申请号 GB20130004187 申请日期 2013.03.08
申请人 CONTROL TECHNIQUES LTD 发明人
分类号 H02M1/00;H02M1/32;H02M7/5387 主分类号 H02M1/00
代理机构 代理人
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