发明名称 Methods and apparatus for verifying the operation of a circuit design
摘要 <p>A method and apparatus are disclosed for debugging circuit designs having random access memory (RAM) therein. The circuit design is emulated on a hardware logic emulator or software simulator. The RAM can be rewound or reconstructed to a previous state, and then replayed. The RAM can also be reconstructed to a state in which the RAM was maintained at some point during a trace window.</p>
申请公布号 EP1450278(B1) 申请公布日期 2013.04.24
申请号 EP20040005293 申请日期 2004.01.23
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 BELETSKY, PLATON;KFIR, ALON;LIN, TSAIR-CHIN
分类号 G06F11/14;G06F17/50 主分类号 G06F11/14
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