发明名称 |
Method and apparatus for fast frequency locking in a closed loop based frequency synthesizer |
摘要 |
A synthesizer comprises a first processing unit that receives digital information relating to a required final frequency of the synthesizer and determines a primary frequency value and a corresponding frequency multiplier mode. A primary synthesizer receives the primary frequency value and an external reference frequency signal to generate a signal of the primary frequency. The synthesizer further comprises a second processing unit that receives the primary frequency value, determines a pre-charge voltage value corresponding to the primary frequency value, and transmits the pre-charge voltage value to a delay locked loop in response to a change in the primary frequency value. The delay locked loop receives the signal of primary frequency and the pre-charge value. The DLL is pre-charged to the pre-charge voltage value for a predetermined time, by opening and closing the delay locked loop to obtain fast locking of the synthesizer.
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申请公布号 |
US8427205(B1) |
申请公布日期 |
2013.04.23 |
申请号 |
US201113328240 |
申请日期 |
2011.12.16 |
申请人 |
NAGARAJ GEETHA B.;CAFARO NICHOLAS G.;STENGEL ROBERT E.;TALWALKAR SUMIT A.;MOTOROLA SOLUTIONS, INC. |
发明人 |
NAGARAJ GEETHA B.;CAFARO NICHOLAS G.;STENGEL ROBERT E.;TALWALKAR SUMIT A. |
分类号 |
H03B21/00;H03L7/00 |
主分类号 |
H03B21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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