发明名称 |
Methods and systems for first occurence debugging |
摘要 |
An embodiment relates generally to an apparatus for debugging. The apparatus includes a memory configured to store data and an arithmetic logic unit configured to perform logical and arithmetic operations. The apparatus also includes a control unit configured to interface with the memory and arithmetic logic unit and to decode instructions. The control unit is configured to write a data state designated to be overwritten by a currently executing instruction to a buffer allocated in the memory in response to a trace debug flag being set. |
申请公布号 |
US8429460(B2) |
申请公布日期 |
2013.04.23 |
申请号 |
US20100890260 |
申请日期 |
2010.09.24 |
申请人 |
DREPPER ULRICH;RED HAT, INC. |
发明人 |
DREPPER ULRICH |
分类号 |
G06F11/00 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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