| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a CDR circuit capable of detecting a false lock state, and resetting the false lock state. <P>SOLUTION: The CDR circuit includes a clock recovery circuit which generates a first clock as a data sampling clock for sampling the data of a received data signal, and a second clock as an edge sampling clock for sampling the edge of the received data signal, and adjusts the phases of the first and second clocks. The CDR circuit includes a phase detection circuit which outputs the results of the sampling of the received data signal at the first clock as data sampling results, and outputs the results of the sampling of the received data signal at the second clock as edge sampling results. The CDR circuit includes a result comparison circuit which compares the edge sampling results with a preset data pattern, and when the edge sampling results match the preset data pattern, determines that it is in false lock state and outputs a false lock state detection signal. <P>COPYRIGHT: (C)2013,JPO&INPIT |
