发明名称 Field effect transistor capable of reducing shift of threshold voltage
摘要 A problem is arisen in conventional J-FETs that a shifting in a threshold voltage (VT) is generated before or after an energization with a gate current. A junction gate field effect transistor (J-FET) according to the present invention includes an undoped InGaAs channel layer 5, which is capable of accumulating carrier of a first conductivity type, a p+ type GaAs layer 17 (semiconductor layer), which is provided on the undoped InGaAs channel layer 5, and contains an impurity of a second conductivity type, and a gate electrode 18, which is provided on the p+ type GaAs layer 17. Here, the concentration of hydrogen contained in the p+ type GaAs layer 17 is lower than the concentration of the second conductivity type carrier in the p+ type GaAs layer 17.
申请公布号 US8421120(B2) 申请公布日期 2013.04.16
申请号 US20070760899 申请日期 2007.06.11
申请人 BITO YASUNORI;RENESAS ELECTRONICS CORPORATION 发明人 BITO YASUNORI
分类号 H01L29/66 主分类号 H01L29/66
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