发明名称 LAYOUT OF MEMORY CELLS
摘要 A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.
申请公布号 US2013088925(A1) 申请公布日期 2013.04.11
申请号 US201113267235 申请日期 2011.10.06
申请人 CHANG JACKLYN;TAO DEREK C.;TANG YUKIT;HSU KUOYUAN (PETER);TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 CHANG JACKLYN;TAO DEREK C.;TANG YUKIT;HSU KUOYUAN (PETER)
分类号 G11C7/10 主分类号 G11C7/10
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