发明名称 System and method for high precision clock recovery over packet networks
摘要 An improved system and method for achieving high precision clock recovery, i.e. reconstruction of the clock signal having the same frequency, over a packet switched network. The proposed method utilizes a minimum network delay approach, which overcomes the problems caused by delay variation of the network and filters out network jitter, such as noise jitter and other singular anomalies causing latency deviations. Minimum network delay is defined herein as the time delay in which a packet remains in the network under assumption that all transmission queues through which the packet passes are empty. The proposed system and method perform clock recovery by including an improvement in the form of dynamically varying thresholds. Reconstruction of the clock signal is performed in accordance with the minimum network delay estimation based on an adjustable threshold, i.e., the latency change threshold, which increases when the noise threshold increases and decreases when the noise threshold decreases. This allows detection of latency changes in accordance with the dynamically varying network conditions and avoids false latency change detections.
申请公布号 US8416814(B2) 申请公布日期 2013.04.09
申请号 US20100705660 申请日期 2010.02.15
申请人 SHTERN ALON;TAL ALEX;KRONENTHAL GUY;KORN RAZ;BARAK ZIV;SHASHA OSNAT;AXERRA NETWORKS, LTD. 发明人 SHTERN ALON;TAL ALEX;KRONENTHAL GUY;KORN RAZ;BARAK ZIV;SHASHA OSNAT
分类号 H04J3/06 主分类号 H04J3/06
代理机构 代理人
主权项
地址