发明名称 Successive approximation register-analog digital converter and receiver
摘要 An SAR-ADC includes input and reference terminals, first and second capacitor sets, a dummy capacitor, a comparator, a switch, and a logic. The first and second capacitor sets include first and second capacitors, respectively. The first capacitor has a first capacitance. The second capacitor has a second capacitance. The dummy capacitor has a third capacitance. The comparator compares an output voltage with a ground voltage and outputs a digital output code in accordance with a difference between the output and ground voltages. The switch is connected among the first capacitors of the first and second capacitor sets, and the reference terminal. The logic turns the switch based on the digital output code. The input terminal is located between the first and second capacitors of the first capacitor set. The second capacitor of the first capacitor set is located between the first and second capacitors of the second capacitor set.
申请公布号 US8416115(B2) 申请公布日期 2013.04.09
申请号 US201113035202 申请日期 2011.02.25
申请人 ARAKI MAI;FURUTA MASANORI;KABUSHIKI KAISHA TOSHIBA 发明人 ARAKI MAI;FURUTA MASANORI
分类号 H03M1/12;H03M1/80 主分类号 H03M1/12
代理机构 代理人
主权项
地址
您可能感兴趣的专利