SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDE

摘要

Disclosed herein is a semiconductor device that includes a verification circuit and an error processing circuit. the verification circuit verifies second bits of an external command to generate the verification result signal. The error processing circuit supplies a follow-up signal to a bank control circuit after a lapse of a first period and a second period when the verification result signal indicates a fail state during a write operation. The first period corresponds to a write latency indicating a period between when a write command is generated and when a data associated with the write command is supplied from outside. The second period corresponds to a write recovery latency indicating a period between when the bank control circuit issues a write execution signal to start writing the data to memory cells and when the write operation is completed.