发明名称 METHOD AND APPARATUS OF MINIMIZING EXTRINSIC PARASITIC RESISTANCE IN 60GHZ POWER AMPLIFIER CIRCUITS
摘要 Very high frequency circuits suffer from parasitic resistances. At 60 GHz, conventional layout techniques can introduce loss into the circuit at critical locations. One critical interconnect between the output of a pre-driver and the gate of the final output stage causes 1 or 2 dB of loss due to the layout. By minimizing the number of via contacts, this conventional loss can be recovered using this new layout technique. In addition, a tap point of a via stack is used to modify the resonant characteristics of the interconnect. Finally, cross coupled devices in a resonant circuit are used to reduce the common mode noise at the expense of the common mode gain.
申请公布号 WO2013043957(A2) 申请公布日期 2013.03.28
申请号 WO2012US56466 申请日期 2012.09.21
申请人 TENSORCOM, INC. 发明人 SOE, ZAW
分类号 H03B1/00;H03F3/45 主分类号 H03B1/00
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