发明名称 |
MANAGING IN-LINE STORE THROUGHPUT REDUCTION |
摘要 |
Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At least one blocking condition is determined to have occurred at the store request queue. Multiple non-store requests and a set of store requests associated with a remaining set of processing cores in the multiple processing cores are dynamically blocked from accessing a memory cache in response to the blocking condition having occurred.
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申请公布号 |
US2013080705(A1) |
申请公布日期 |
2013.03.28 |
申请号 |
US201213682136 |
申请日期 |
2012.11.20 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BERGER DEANNA P.;FEE MICHAEL F.;JONES CHRISTINE C.;ORF DIANA L.;SONNELITTER, III ROBERT J. |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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