Implementing switching factor reduction in LBIST

摘要

A method and circuit are provided for implementing switching factor reduction in Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides. Switching factor reduction logic is coupled to a Pseudo-Random Pattern Generator (PRPG) providing channel input patterns to a plurality of LBIST channels used for the LBIST diagnostics. The switching factor reduction logic selectively provides controlled channel input patterns for each of the plurality of channels.