发明名称 |
Output buffer circuit, input buffer circuit, and input/output buffer circuit |
摘要 |
An output buffer circuit in accordance with an embodiment comprises a plurality of buffer circuits, each of the buffer circuits including a transistor operative to change an output signal of an output terminal in response to a change in an input signal, the output buffer circuit being configured to enable the plurality of buffer circuits to be driven selectively. Each of the plurality of buffer circuits includes a plurality of output transistors having respective current paths formed in parallel to one another between a fixed voltage terminal supplying a certain fixed voltage and an output terminal, and being selectively rendered in an operable state in accordance with a control signal provided from external. The plurality of output transistors included in each of the plurality of buffer circuits are formed having a certain size ratio. |
申请公布号 |
US8405432(B2) |
申请公布日期 |
2013.03.26 |
申请号 |
US20100963114 |
申请日期 |
2010.12.08 |
申请人 |
KOYANAGI MASARU;KAJIYAMA YASUFUMI;FUKUDA RYO;MATSUOKA FUMIYOSHI;SUEMATSU YASUHIRO;KABUSHIKI KAISHA TOSHIBA |
发明人 |
KOYANAGI MASARU;KAJIYAMA YASUFUMI;FUKUDA RYO;MATSUOKA FUMIYOSHI;SUEMATSU YASUHIRO |
分类号 |
H03K3/01 |
主分类号 |
H03K3/01 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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