CDR WITH DIGITALLY CONTROLLED LOCK TO REFERENCE

摘要

In described embodiments, a receiver includes a clock and data recovery (CDR) circuit with a voltage control oscillator (VCO) having proportional and integral loop control, and a Lock to Reference (L2R) mode circuit using Phase and Frequency Detector (PFD) control of the VCO during the absence of input data to the CDR. A regular CDR second order loop incorporating PFD control of the VCO during the absence of input data to the CDR achieves relatively rapid lock to reference when compared to counter-based lock to reference mode of operation.