发明名称 Clock generator intermittently generating synchronous clock
摘要 A clock generator includes a counter receiving a reference clock signal to generate a timing signal based on the reference clock signal, and a plurality of intermittent clock generating units each coupled to a storage unit thereof storing a bit strings data, each of the intermittent clock generating units receiving the reference clock signal and the timing signal. Each of the intermittent clock generating units masks a clock pulse of the reference clock signal based on the bit string data stored in the storage unit thereof to output an intermittent clock signal in response to the timing signal.
申请公布号 US8400202(B2) 申请公布日期 2013.03.19
申请号 US201113064596 申请日期 2011.04.01
申请人 MINAKI TAKAHIRO;RENESAS ELECTRONICS CORPORATION 发明人 MINAKI TAKAHIRO
分类号 G06F1/04;H03K3/00 主分类号 G06F1/04
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