| 摘要 |
In general, embodiments of the present invention provide a double data rate (DDR) controller having a shared address and separate data error direction for DDR3 direct memory access (DMA). In a typical embodiment, the architecture described herein comprises a fields programmable gate array (FPGA) having a single memory controller coupled to a data multiplexer (MUX). Groups/sets of memory having individual dual inline memory modules (DIMMs) are coupled to the memory controller and the data MUX. Data flows between the DIMMs and the data multiplexer, while address and control information flows between the DIMMs and the memory controller.
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