| 摘要 |
A method for decreasing polysilicon gate resistance in a carbon co-implantation process which includes: depositing a first salicide block layer on a formed gate of a MOS device and etching it to form a first spacer of a side surface of the gate of the MOS device; performing a P-type heavily doped boron implantation process and a thermal annealing treatment, so as to decrease the resistance of the polysilicon gate; removing said first spacer, performing a lightly doped drain process, and performing a carbon co-implantation process at the same time, so as to form ultra-shallow junctions at the interfaces between a substrate and source region and drain region below the gate; re-depositing a second salicide block layer on the gate and etching the mask to form a second spacer; forming a self-aligned silicide on the surface of the MOS device. The invention can decrease the resistance of the P-type polysilicon gate.
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