发明名称 LAYOUT METHOD, LAYOUT APPARATUS, AND PROGRAM FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 A layout method, upon performing layout of layer blocks each including internal elements, with respect to mounting area where internal element resources, to which internal elements can be assigned, are arranged, comprises: arranging, when first layer block and second layer block overlap in overlapping area, first layer block and the second layer block such that sum of number of first internal elements included in the overlapping area, among internal elements of first layer block, and number of second internal elements included in the overlapping area, among internal elements of second layer block, is not greater than number of internal element resources included in the overlapping area; and assigning the internal element resources included in the overlapping area to first layer block and second layer block, in accordance with ratio of number of first internal elements to number of second internal elements.
申请公布号 US2013061194(A1) 申请公布日期 2013.03.07
申请号 US201213604058 申请日期 2012.09.05
申请人 HANDA MITSURU;RENESAS ELECTRONICS CORPORATION 发明人 HANDA MITSURU
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址