INTEGRATED CIRCUIT, TEST DEVICE FOR INTEGRATED CIRCUIT, AND TEST METHOD FOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To acquire a failure occurrence position in a redundant memory of an integrated circuit when the redundant memory is tested.

SOLUTION: A testing device for integrated circuit includes: the redundant memory 30 having a spare memory cell; a generation section 41 for generating a test pattern applied to the redundant memory 30 and an anticipated value of data to be output from the redundant memory 30 when the test pattern is applied to the redundant memory 30; a comparison section 42 for comparing the anticipated value generated by the generation section 41 with data to be output from the redundant memory 30 when the test pattern generated by a first generation section 41 is applied to the redundant memory 30; a storage section 10 for storing a comparison result of the comparison section 42; and a write control section 50A for writing the comparison result into the storage section 10 in associating with the positional information of the redundant memory 30 about which the comparison result is obtained when the comparison result by the comparison section 42 shows consistency, while suppressing the writing of the comparison result into the storage section 10 when the comparison result by the comparison section 42 shows inconsistency.

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