| 摘要 |
When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally degraded by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.
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