发明名称 Memory architecture and system, and interface protocol
摘要 A system includes a first integrated circuit. The first integrated circuit includes a direct memory access (DMA) circuit, a first random access memory (RAM) that is accessed by the DMA circuit using DMA, a data/command terminal that communicates with the DMA circuit and that receives a selection signal, and an M-bit data terminal that communicates with the DMA circuit and that receives a write command during a first period when the selection signal has a first state, a write address during a second period when the selection signal has a second state that is different than the first state, and write data during T third periods when the selection signal has the second state. M is an integer greater than one and T is an integer greater than zero. The first period, the second period, and the T third periods are non-overlapping.
申请公布号 US8386735(B1) 申请公布日期 2013.02.26
申请号 US20080220607 申请日期 2008.07.25
申请人 MARVELL INTERNATIONAL LTD.;AZIMI SAEED;CHANG PO-CHIEN 发明人 AZIMI SAEED;CHANG PO-CHIEN
分类号 G06F12/00;G06F3/06;G06F12/08;G06F13/00;G06F13/28;G06F13/40;G11C15/00 主分类号 G06F12/00
代理机构 代理人
主权项
地址