| 摘要 |
A phase delay element coupled to an output of A multiplexor and a first input of the multiplexor. A reference clock line is coupled to a second input of the multiplexor. A selector that is coupled to a selector input of the multiplexor. A signal divider element coupled to an output of the phase delay element. A variable delay controller is coupled to a) the output of the variable delay controller; b) at least one output of the variable delay controller. An integrated phase detector and charge pump element (PDCHP) is coupled to at least: a) an output of the variable delay controller; and b) the selector; c) and a first and second output of the divider element. A capacitor is coupled to an output of the PDCHP, wherein the capacitor is also coupled to a controller input of the phase delay element.
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