发明名称 Chip Stack Packages Having Aligned Through Silicon Vias of Different Areas
摘要 A chip stack package includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The first semiconductor chip includes a first through silicon via that extends through the first semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and includes a second through silicon via that extends through the second semiconductor chip. The second through silicon via is disposed on the first through silicon via, and has a cross-sectional area smaller than that of the first through silicon via. The third semiconductor chip is stacked on the first semiconductor chip, and includes a third through silicon via that extends through the third semiconductor chip. The third through silicon via is disposed on the second through silicon via, and has a cross-sectional area smaller than that of the second through silicon via.
申请公布号 US2013037944(A1) 申请公布日期 2013.02.14
申请号 US201213568367 申请日期 2012.08.07
申请人 SAMSUNG ELECTRONICS CO., LTD.;LEE BYUNG-HYUN;LEE HOON 发明人 LEE BYUNG-HYUN;LEE HOON
分类号 H01L23/488 主分类号 H01L23/488
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