| 摘要 |
A memory controller takes in the first to (N−1)th pieces of data respectively in synchronization with the second to Nth return read clocks. The memory controller takes in the Nth piece of data from stop of output of the Nth read clock and before a first predetermined time. The memory controller sets an output period of the Nth read clock to be longer than an output period of each of the first to (N−1)th read clocks.
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