| 摘要 |
A semiconductor memory apparatus includes a memory cell, a data transfer unit configured to adjust an access to the memory cell according to a voltage level of a selection signal, a selection signal output unit configured to output the selection signal having a first control voltage level in a data write mode and a second control voltage level in a data read mode. A data detection unit may also be configured to detect a voltage formed by a sensing current supplied to the memory cell through the data transfer unit in the data read mode, and output read data according to the detection result, wherein the second control voltage level is lower than the first control voltage level.
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