| 摘要 |
The throughput of a CPU is improved in a system wherein a system controller, which connects a plurality of CPUs, controls the cache synchronization. A system having a system controller (12) which connects a plurality of CPU units (10-0 - 10-3) with differing cache memory sizes and which controls cache synchronization, the system comprises a cache synchronization unit (54) which monitors the address conflict between a first generated request and a second generated request; and a setting unit (56) which sets the conflict monitoring range of the first generated request and the second generated request for each size of cache memory of each CPU unit. Therefore even if CPU units of differing cache sizes are mixed together, the throughput of the CPU unit with the largest cache size can be improved. |
