| 摘要 |
PURPOSE:To atain remarkably low power consumption, by employing the 1st logical gate connecting a plurality of n-channel MOSFETs in series, and the 2nd logical gate connecting a plurality of p-channel MOSFETs in series. CONSTITUTION:N-channel MOSFETs Q1-Q4 are formed in a P-well and P-channel MOSFETs Q5-Q8 are formed on a P substrate. In using a positive power supply voltage VDD(+), the P substrate is biased with a positive power supply voltage. Further, a power supply voltage terminal VSS(-) is biased at zero volt. Thus, a load MOSFETQ4 is provided at the power supply voltage VDD(+) and a load MOSFETQ8 is provided at the voltage terminal VSS(-). Thus, in this NAND circuit, no DC current can flow through the load MOSFETQ4 and a logical block unless input signals (a)-(c) are all ''1''. |
