发明名称 PARALLEL RATE CONTROL FOR DIGITAL VIDEO ENCODER WITH MULTI-PROCESSOR ARCHITECTURE AND PICTURE-BASED LOOK-AHEAD WINDOW
摘要 A method of operating a multi-processor video encoder by determining a target size corresponding to a preferred number of bits to be used when creating an encoded version of a picture in a group of sequential pictures making up a video sequence. The method includes the steps of calculating a first degree of fullness of a coded picture buffer at a first time, operating on the first degree of fullness to return an estimated second degree of fullness of the coded picture buffer at a second time, and operating on the second degree of fullness to return an initial target sized for the picture. The first time corresponds to the most recent time an accurate degree of fullness of the coded picture buffer can be calculated and the second time occurs after the first time.
申请公布号 KR101228192(B1) 申请公布日期 2013.01.30
申请号 KR20077015775 申请日期 2005.11.21
申请人 发明人
分类号 H04J3/16;H04N7/12;H04N11/02 主分类号 H04J3/16
代理机构 代理人
主权项
地址