发明名称 VECTOR NORMALISING APPARATUS
摘要 FIELD: information technology.SUBSTANCE: invention is meant for use in high-performance computer systems, particularly digital signal processing systems operating in real time, fast process control systems, in personal computers as a means of enhancing performance, realised as a subcircuit in an arithmetic processor or as part of a separate device (special-purpose processor). The apparatus has n normalisation units, each having shift and adder-subtractor circuits and a radical inversion unit having shift circuits, shift code generating circuits, circuits for generating the code for setting the operating mode of adders-subtractors, double adders-subtractors.EFFECT: high rate of normalising an n-dimensional vector.1 dwg
申请公布号 RU2473961(C1) 申请公布日期 2013.01.27
申请号 RU20110150584 申请日期 2011.12.12
申请人 BABENKO VIKTOR NIKOLAEVICH 发明人 BABENKO VIKTOR NIKOLAEVICH
分类号 G06F17/16 主分类号 G06F17/16
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