发明名称 |
SEMICONDUCTOR DEVICE, SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR SUBSTRATE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD |
摘要 |
<P>PROBLEM TO BE SOLVED: To reduce source/drain region resistance or contact resistance of an nMISFET of a group III-V semiconductor and a pMISFET of a group IV semiconductor, which are formed simultaneously in the same process on a single substrate. <P>SOLUTION: A semiconductor device comprises a first-channel first MISFET formed on a first semiconductor crystal layer and a second-channel second MISFET formed on a second semiconductor crystal layer. A first source and a first drain of the first MISFET, and a second source and a second drain of the second MISFET are composed of the same conductive material and a work function Φ<SB POS="POST">M</SB>of the conductive material satisfies at least one of relationships represented as a formula 1 and a formula 2, respectively:(Formula 1) ϕ<SB POS="POST">1</SB><Φ<SB POS="POST">M</SB><ϕ<SB POS="POST">2</SB>+E<SB POS="POST">g2</SB>; (Formula 2) ¾Φ<SB POS="POST">M</SB>-ϕ<SB POS="POST">1</SB>¾≤0.1 eV and ¾(ϕ<SB POS="POST">2</SB>+E<SB POS="POST">g2</SB>)-Φ<SB POS="POST">M</SB>¾≤0.1 eV, where ϕ<SB POS="POST">1</SB>represents electron affinity of an N-type semiconductor crystal layer, and ϕ<SB POS="POST">2</SB>and E<SB POS="POST">g2</SB>represent electron affinity and a forbidden band width of a P-type semiconductor crystal layer, respectively. <P>COPYRIGHT: (C)2013,JPO&INPIT |
申请公布号 |
JP2013016791(A) |
申请公布日期 |
2013.01.24 |
申请号 |
JP20120131890 |
申请日期 |
2012.06.11 |
申请人 |
SUMITOMO CHEMICAL CO LTD;UNIV OF TOKYO;NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL & TECHNOLOGY |
发明人 |
TAKADA TOMOYUKI;YAMADA HISASHI;HATA MASAHIKO;TAKAGI SHINICHI;MAEDA TATSURO;URABE YUJI;YASUDA TETSUJI |
分类号 |
H01L21/8238;H01L21/02;H01L21/20;H01L21/28;H01L21/336;H01L27/08;H01L27/092;H01L27/12;H01L29/786 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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