发明名称 |
DOUBLE PATTERNING METHODOLOGY |
摘要 |
Provided is a method of fabricating a semiconductor device. The method includes providing an integrated circuit layout plan, the integrated circuit layout plan containing a plurality of semiconductor features. The method includes selecting a subset of the features for decomposition as part of a double patterning process. The method includes designating a relationship between at least a first feature and a second feature of the subset of the features. The relationship dictates whether the first and second features are assigned to a same photomask or separate photomasks. The designating is carried out using a pseudo feature that is part of the layout plan but does not appear on a photomask. The method may further include a double patterning conflict check process, which may include an odd-loop check process.
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申请公布号 |
US2013024822(A1) |
申请公布日期 |
2013.01.24 |
申请号 |
US201113188071 |
申请日期 |
2011.07.21 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.;HSIEH KEN-HSIEN;CHEN HUANG-YU;WANG JHIH-JIAN;TSAI CHENG KUN;OU TSONG-HUA;HUANG WEN-CHUN;LIU RU-GUN |
发明人 |
HSIEH KEN-HSIEN;CHEN HUANG-YU;WANG JHIH-JIAN;TSAI CHENG KUN;OU TSONG-HUA;HUANG WEN-CHUN;LIU RU-GUN |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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地址 |
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