| 摘要 |
PROBLEM TO BE SOLVED: To reduce the hardware scale in comparison with a memory configuration and to enhance the processing speed by configuring an interleaver with (N+1) sets of counters and N sets of adders, where N is number of stages by the MIL method, without the need for many number of memories. SOLUTION: This interleaver is provided with an address generating section consisting of counters 12, 13, 16, 19 that can set counts 14, 17, 20 and offsets 15, 18, 21 of count-up without the need for a plurality of memory areas and of adders 22, 23, 24 summing outputs of the counters to allow a memory 11 to provide an output of data bits according to a generated address, and the interleaver obtains an interleave output where data units being divisions of transmission data are rearranged according to prescribed rules.
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