Process for manufacturing semiconductor integrated electronic memory devices having a virtual ground cells matrix

摘要

A process for manufacturing electronic semiconductor integrated memory devices having a virtual ground and comprising at least a matrix of floating gate memory cells (1), the matrix being formed on a semiconductor substrate (2) with a plurality of continuous bit lines (BL) extending across the substrate (2) as discrete parallel strips, comprising at least the following steps: growing an oxide layer (3) over the matrix region; depositing the semiconductor throughout with a stack structure which comprises a first conductor layer (4), first dielectric layer (5), and second conductor layer (6): depositing a second dielectric layer (7); defining floating gate regions (10) by photolithography using a mask of "POLY1 along a first direction", to thereby define, in said dielectric layer (7), a plurality of parallel strips (8) which delimit a first dimension of floating gate regions; etching away said dielectric layer (7) to define said plurality of parallel dielectric strips (8); photolithographing by means of a mask of "POLY1 along a second direction" to define a plurality of dielectric islands (9) in said plurality of parallel strips (8); etching away said dielectric layer (7) to define the plurality of islands (9); etching away said stack structure (4,5,6) and the thin gate oxide layer (3) to define gate regions (10) of the matrix cells using said oxide island (9). <IMAGE> <IMAGE>