| 摘要 |
PURPOSE: A repair circuit of semiconductor memory device with improved reliability, which has an improved reliability as using an electrically activated fuse. CONSTITUTION: The repair circuit(10) comprises a PMOS transistor(PM), an NMOS transistor(NM0), four fuse parts(12a-12d) and a logic device(NAND). The PMOS transistor precharges a repair node(N0) to a power supply voltage(VCC) level if a precharge signal(PRCH_TST) is activated to a low level. The NMOS transistor is turned on in response to a repair address(R_ADDR). The first fuse part(12a) includes a fuse(FSa) and four NMOS transistors(NM1a,NM2a,NM3a,NM4a) and an exclusive OR gate(XORa). To activate the fuse, a fuse voltage(V_FUSE) is applied to the first node(N1a), and a fuse voltage applying signal(V_FUSE_ENa) inputted to a gate of the first NMOS transistor(NM1a) is activated. Then, the second node(N2a) has the fuse voltage level. A voltage(HALF_V_FUSE) corresponding to a half of the fuse voltage is applied to each gate of the second and the third and the fourth NMOS transistor, which are for preventing an insulation film of other devices from being broken. If the second node(N2a) becomes the fuse voltage level, an insulation film of the fuse is broken and the fuse is short and a voltage difference between both nodes becomes zero.
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