发明名称 LEVEL CONVERSION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a level conversion circuit in which a duty fluctuation is small. SOLUTION: A positive phase input is inputted to positive phase CMOS inverters 21 and 22, and the CMOS inverters 21 and 22 output an inverted output. Positive phase emitter followers 23 and 24 shift the level of an output of the positive phase CMOS inverters. A negative phase input of a CMOS level is inputted to negative phase CMOS inverters 25 and 26, and the CMOS inverters 25 and 26 output an inverted output. Negative phase emitter followers 27 and 28 shift the level of an output of the negative phase CMOS inverters. Furthermore, a bias source 60 can prevent the reverse biases of bipolar transistors 23 and 27 constituting the emitter followers by applying a bias voltage to the source 22 of an NMOS constituting the positive phase CMOS inverters, the source of the NMOS 26 constituting the negative phase CMOS inverters, the emitter resistance 24 of the positive phase emitter followers and the emitter resistance 28 of the negative phase emitter followers.
申请公布号 JP2002164778(A) 申请公布日期 2002.06.07
申请号 JP20010299503 申请日期 2001.09.28
申请人 HITACHI LTD;HITACHI COMMUN SYST INC;HITACHI ULSI SYSTEMS CO LTD 发明人 MAEDA FUMIHIDE;IRIE HIRONORI;YAMASHITA SOICHI;HAYANO MASAJI
分类号 H03K5/02;H03K19/0175;H03K19/018;(IPC1-7):H03K19/017 主分类号 H03K5/02
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