发明名称 Hash function for hardware implementations
摘要 A logic block is presented that generates avalanche criterion hash values using minimal logic. The logic block includes a first exclusive-OR function, a second exclusive-OR function, and an OR function. The first exclusive-OR function receives two input bits from a data packet and generates a linear output value based upon exclusive disjunction between the two input bits. The OR function receives two different input bits from the data packet and generates a first nonlinear output value based upon logical disjunction between the two different input bits. The second exclusive-OR function receives the linear output value and the first nonlinear output value, and generates a second nonlinear output value based upon exclusive disjunction between the linear output value and the first nonlinear output value. In turn, the second nonlinear output value is utilized to generate a hash value for the data packet.
申请公布号 US8359346(B2) 申请公布日期 2013.01.22
申请号 US20090612757 申请日期 2009.11.05
申请人 FREESCALE SEMICONDUCTOR, INC.;GRAYSON BRIAN C.;ROBINSON LEICK D.;MENCHACA BENJAMIN M. 发明人 GRAYSON BRIAN C.;ROBINSON LEICK D.;MENCHACA BENJAMIN M.
分类号 G06F7/00 主分类号 G06F7/00
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