发明名称 |
PROGRAMMABLE LOGIC DEVICE |
摘要 |
<P>PROBLEM TO BE SOLVED: To improve the processing speed and lower the power consumption of a programmable logic device that can maintain a connection condition of a logic circuit even during the stop of supply of power source voltage. <P>SOLUTION: A programmable logic device comprises: a plurality of arithmetic circuits whose logic state can be switched; a configuration state switching circuit for switching the logic state of the arithmetic circuit; a power source control circuit for switching between the supply and the stop of power source voltage for the arithmetic circuit; a state storing circuit for storing the logic state of the arithmetic circuits and the state of the power source voltage; and an arithmetic state control circuit for controlling the configuration state switching circuit and the power source control circuit in accordance with stored information of the state storing circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the arithmetic circuit and the configuration state switching circuit, and the conduction state of the transistor is maintained while the power source voltage from the power source control circuit is stopped. <P>COPYRIGHT: (C)2013,JPO&INPIT |
申请公布号 |
JP2013013067(A) |
申请公布日期 |
2013.01.17 |
申请号 |
JP20120114200 |
申请日期 |
2012.05.18 |
申请人 |
SEMICONDUCTOR ENERGY LAB CO LTD |
发明人 |
YONEDA SEIICHI;KOYAMA JUN;SHIONOIRI YUTAKA;ENDO MASAMI;DENPO HIROKI;NISHIJIMA TATSUJI;KOBAYASHI HIDETOMO;OSHIMA KAZUAKI |
分类号 |
H03K19/173;H01L21/82;H01L29/786;H03K3/356 |
主分类号 |
H03K19/173 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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