发明名称 |
Synchronous data processing system for reliable transfer of data irrespective of propagation delays and process, voltage and temperature (PVT) variations |
摘要 |
A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer.
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申请公布号 |
US8355294(B2) |
申请公布日期 |
2013.01.15 |
申请号 |
US201113050932 |
申请日期 |
2011.03.18 |
申请人 |
FREESCALE SEMICONDUCTOR, INC;MAKWANA PRAKASH;SINGH PRABHJOT |
发明人 |
MAKWANA PRAKASH;SINGH PRABHJOT |
分类号 |
G11C8/18 |
主分类号 |
G11C8/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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