| 摘要 |
A Decision Feedback Equalizer (DFE) capable of preventing incremental increases of a jitter of a recovered clock and reduction of a voltage margin of decided data due to delay of feedback data. The DFE includes a combiner for combining received data with feedback data and outputting the combined data as equalization data, a decision circuit for deciding recovery data by receiving the equalization data, a feedback loop for supplying the recovery data to the combiner as feedback data and a clock recovery circuit for removing a delay data component from the equalization data through the feedback loop, recovering a clock with respect to the other equalization data except the delay data component and supplying the recovered clock for decision operation of the decision circuit.
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