| 摘要 |
The invention relates to a method and a circuit configuration for checking an m of n code. The method uses a code checker with which at least one code reducer (304, 306, 308) is associated, wherein a reduction of the code word width to half thereof is carried out by means of the at least one code reducer (304, 306, 308), until a 1 of x (x = n/2, n/4, n/8...) code or another code that cannot be further reduced in said manner is present, wherein each stage of the code reducer (304, 306, 308) is additionally connected to different bits of a counter, wherein the 1 of x code or the code that cannot be further reduced is checked and the signal pairs of each stage are additionally checked. |
